Design of Low Phase Noise Low Power CMOS Phase Locked Loops

Phase locked loop (PLL) is one of the most critical devices in modern electronic systems. PLLs are widely used as clock generator or frequency synthesis in communication systems, computers, radio and other electronic applications. Phase noise represents the phase variations of a PLL output signal and is the most important characteristic of PLLs because it reflects the stability of PLL systems. Low power consumption is always desired for any electronic products today. CMOS technology is the most common process to make integrated-circuits. In this thesis, we focus on the design of low phase noise and low power CMOS PLL integrated circuits. Understanding phase noise generation mechanism in PLLs is the basis for low phase noise design. Therefore, phase noise contributed by each components in PLLs are studied at first. Voltage controlled oscillator (VCO) is a critical component and the main noise contributor in a PLL. A detailed phase noise analysis for LC-tank based VCO and ring oscillator VCO, which are the most implemented VCO types, is performed. Then, the techniques for designing low phase noise and low power VCO and PLL are studied. Two PLL prototype chips are designed and fabricated in CMOS technology to demonstrate the design techniques for low phase noise and low power PLL. The first PLL is applied as clock generator in a LVDS transmitter and implemented into the AMS 0.35 μm CMOS process technology. A novel low noise charge-pump is implemented in this PLL to achieve low phase jitter together with a VCO based on fully differential ring oscillator, a PFD based on dynamic logic circuit, and a passive loop filter. The measurement results of the PLL chip exhibit excellent phase jitter-power consumption product and wide lock range. The second PLL chip is used in an atomic clock system to provide a reference frequency of 1.5 GHz. The test chip is implemented into